絲?。?strong>8541；Package：VSSOP；SN74AC8541 Octal Buffers or Drivers With 3-State Outputs

1 Features ? Wide operating range of 1.5V to 6V ? Inputs accept voltages up to 6V ? Continuous ±24mA output drive at 5V ? Supports up to ±75mA output drive at 5V in short bursts ? Drives 50Ω transmission lines ? Maximum tpd of 6ns at 5V, 50pF load 2 Applications ? Enable or disable a di

文件：1.71108 Mbytes 頁數(shù)：28 Pages

TI

德州儀器

絲?。?strong>8541；Package：SOT23-5；OPERATION INSTRUCTION

文件：2.44234 Mbytes 頁數(shù)：21 Pages

COREBAI

芯佰微

絲?。?a target="_blank" title="Marking" href="/85411ail/marking.html">85411AIL；Package：SOIC；Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES ? Two differential LVDS outputs ? One differential CLK, nCLK clock input ? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? Maximum output frequency: 650MHz ? Translates any single ended input signal to LVDS levels with resistor

文件：386.46 Kbytes 頁數(shù)：16 Pages

RENESAS

瑞薩

絲印：85411AIL；Package：SOIC；Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES ? Two differential LVDS outputs ? One differential CLK, nCLK clock input ? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? Maximum output frequency: 650MHz ? Translates any single ended input signal to LVDS levels with resistor

文件：386.46 Kbytes 頁數(shù)：16 Pages

RENESAS

瑞薩

絲?。?a target="_blank" title="Marking" href="/85411alf/marking.html">85411ALF；Package：SOIC；Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES ? Two differential LVDS outputs ? One differential CLK, nCLK clock input ? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? Maximum output frequency: 650MHz ? Translates any single ended input signal to LVDS levels with resistor

文件：386.95 Kbytes 頁數(shù)：16 Pages

RENESAS

瑞薩

絲印：85411ALF；Package：SOIC；Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES ? Two differential LVDS outputs ? One differential CLK, nCLK clock input ? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? Maximum output frequency: 650MHz ? Translates any single ended input signal to LVDS levels with resistor

文件：386.95 Kbytes 頁數(shù)：16 Pages

RENESAS

瑞薩

絲?。?a target="_blank" title="Marking" href="/85411000/marking.html">85411000；Package：SMA；Diode 600 V 1.5A Surface Mount DO-214AC, SMA

Features Controlled avalanche characteristic High average forward current Compliant to RoHS (exemp. 7a), REACH, Conflict Minerals 1)

文件：768.6 Kbytes 頁數(shù)：3 Pages

DIOTEC

德歐泰克

絲?。?a target="_blank" title="Marking" href="/85411000/marking.html">85411000；Package：SMA；Diode 600 V 1.5A Surface Mount DO-214AC, SMA

Features Controlled avalanche characteristic High average forward current Compliant to RoHS (exemp. 7a), REACH, Conflict Minerals 1)

文件：768.6 Kbytes 頁數(shù)：3 Pages

DIOTEC

德歐泰克

絲印：8541Y；Package：TQFP(PBS)；16-BIT, SINGLE CHANNEL, PARALLEL INPUT DIGITAL-TO-ANALOG CONVERTER WITH RAIL-TO-RAIL VOLTAGE OUTPUT

FEATURES Micropower Operation: 250 μA at 5 V AVDD Power-On Reset to Min-Scale 16-Bit Monotonic Settling Time: 10 μs to ±0.003% FSR 16-Bit Parallel Interface On-Chip Output Buffer Amplifier With Rail-to-Rail Operation Hardware Reset to Min-Scale or Mid-Scale Double-Buffered Architectur

文件：629.74 Kbytes 頁數(shù)：26 Pages

TI

德州儀器

絲印：8541Y；Package：TQFP；16-BIT, SINGLE CHANNEL, PARALLEL INPUT DIGITAL-TO-ANALOG CONVERTER WITH RAIL-TO-RAIL VOLTAGE OUTPUT

FEATURES Micropower Operation: 250 μA at 5 V AVDD Power-On Reset to Min-Scale 16-Bit Monotonic Settling Time: 10 μs to ±0.003% FSR 16-Bit Parallel Interface On-Chip Output Buffer Amplifier With Rail-to-Rail Operation Hardware Reset to Min-Scale or Mid-Scale Double-Buffered Architectur

文件：626.22 Kbytes 頁數(shù)：25 Pages

TI

德州儀器