2:1, Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer

Features ? High speed differential muliplexer. The device can be configured as a 2:1 multiplexer ? Dual 3.3V LVPECL outputs ? Selectable differential CLKx/nCLKx input pairs ? Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Output f

文件：807.3 Kbytes 頁數(shù)：16 Pages

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Propagation delay

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IDT

包裝：散裝 類別：標(biāo)簽，標(biāo)志，護(hù)欄，標(biāo)識 標(biāo)志，銘牌，招貼 描述：B302-3.5X10-WG-T-FIRST AID SIGN

Brady Corporation

包裝：散裝 類別：標(biāo)簽，標(biāo)志，護(hù)欄，標(biāo)識 標(biāo)志，銘牌，招貼 描述：B302-3.5X10-WG-T-FIRST AID SIGN

Brady Corporation

絲印：ICS85356AGIL；Package：TSSOP；2:1, Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer

Features ? High speed differential muliplexer. The device can be configured as a 2:1 multiplexer ? Dual 3.3V LVPECL outputs ? Selectable differential CLKx/nCLKx input pairs ? Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Output f

文件：807.3 Kbytes 頁數(shù)：16 Pages

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絲印：ICS85356AGIL；Package：TSSOP；2:1, Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer

Features ? High speed differential muliplexer. The device can be configured as a 2:1 multiplexer ? Dual 3.3V LVPECL outputs ? Selectable differential CLKx/nCLKx input pairs ? Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Output f

文件：807.3 Kbytes 頁數(shù)：16 Pages

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絲?。?a target="_blank" title="Marking" href="/85356amilf/marking.html">85356AMILF；Package：SOIC；2:1, Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer

Features ? High speed differential muliplexer. The device can be configured as a 2:1 multiplexer ? Dual 3.3V LVPECL outputs ? Selectable differential CLKx/nCLKx input pairs ? Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Output f

文件：807.3 Kbytes 頁數(shù)：16 Pages

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絲?。?a target="_blank" title="Marking" href="/85356amilf/marking.html">85356AMILF；Package：SOIC；2:1, Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer

Features ? High speed differential muliplexer. The device can be configured as a 2:1 multiplexer ? Dual 3.3V LVPECL outputs ? Selectable differential CLKx/nCLKx input pairs ? Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Output f

文件：807.3 Kbytes 頁數(shù)：16 Pages

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2:1 Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer

The 85356I is a dual 2:1 Differential-to-LVPECL Multiplexer. The device has both common select and individual select inputs. When COM_SEL is logic High, the CLKxx input pairs will be passed to the output. When COM_SEL is logic Low, the output is determined by the setting of the SEL0 pin for channel ·High speed differential muliplexer. The device can be configured as a 2:1 multiplexer\n·Dual 3.3V LVPECL outputs\n·Selectable differential CLKx/nCLKx input pairs\n·Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\n·Output frequency: 900MHz (t;

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Package：20-TSSOP（0.173"，4.40mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 時鐘緩沖器，驅(qū)動器 描述：IC CLK MULTPX 2:1 900MHZ 20TSSOP

Renesas Electronics America Inc