絲?。?a target="_blank" title="Marking" href="/ics8535ai31l/marking.html">ICS8535AI31L；Package：TSSOP；LVPECL Fanout Buffer

文件：847.89 Kbytes 頁數(shù)：15 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/ics8535ai31l/marking.html">ICS8535AI31L；Package：TSSOP；LVPECL Fanout Buffer

文件：847.89 Kbytes 頁數(shù)：15 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/ics8535agi31/marking.html">ICS8535AGI31；Package：TSSOP；LVPECL Fanout Buffer

文件：847.89 Kbytes 頁數(shù)：15 Pages

IDT

絲印：8535A21L；Package：TSSOP；Low Skew, 1-to-2 LVCMOS/ LVTTL-to-3.3V LVPECL CLock Generator

Features ? Two differential 3.3V LVPECL outputs ? Selectable CLK0 or CLK1 inputs for redundant and multiple frequency fanout applications ? CLK0 or CLK1 can accept the following input levels: LVCMOS or LVTTL ? Maximum output frequency: 266MHz ? Translates LVCMOS and LVTTL levels to 3.3V LVP

文件：587.44 Kbytes 頁數(shù)：16 Pages

RENESAS

瑞薩

絲?。?a target="_blank" title="Marking" href="/8535a21l/marking.html">8535A21L；Package：TSSOP；Low Skew, 1-to-2 LVCMOS/ LVTTL-to-3.3V LVPECL CLock Generator

Features ? Two differential 3.3V LVPECL outputs ? Selectable CLK0 or CLK1 inputs for redundant and multiple frequency fanout applications ? CLK0 or CLK1 can accept the following input levels: LVCMOS or LVTTL ? Maximum output frequency: 266MHz ? Translates LVCMOS and LVTTL levels to 3.3V LVP

文件：587.44 Kbytes 頁數(shù)：16 Pages

RENESAS

瑞薩

絲?。?a target="_blank" title="Marking" href="/8535a21l/marking.html">8535A21L；Package：TSSOP；Low Skew, 1-to-2 LVCMOS/ LVTTL-to-3.3V LVPECL CLock Generator

文件：394.76 Kbytes 頁數(shù)：15 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/8535a21l/marking.html">8535A21L；Package：TSSOP；Low Skew, 1-to-2 LVCMOS/ LVTTL-to-3.3V LVPECL CLock Generator

文件：394.76 Kbytes 頁數(shù)：15 Pages

IDT

Low Skew,1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL Clock Generator

The 8535-21 is a low skew, high performance 1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer and a member of the family of High Performance Clock Solutions from IDT. The 8535-21 has two single-ended clock inputs. The single-ended clock input accepts LVCMOS or LVTTL input levels and translate them to ? Two differential 3.3V LVPECL outputs\n? Selectable CLK0 or CLK1 inputs for redundant and multiple frequency fanout applications\n? CLK0 or CLK1 can accept the following input levels: LVCMOS or LVTTL\n? Maximum output frequency: 266MHz\n? Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels\n? ;

Renesas

瑞薩

12 Bit, 2-to-1, 3.3V, 2.5V LVPECL Clock Buffer

Renesas

瑞薩

包裝：散裝 類別：標簽，標志，護欄，標識 標志，銘牌，招貼 描述：FIRST AID SIGN

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