絲印：84；Package：LFCSP_UD；Single-Channel, 128-/64-/32-Position, Up/Down, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer

FEATURES Nominal resistor tolerance error: ±8% maximum Wiper current: ±6 mA Rheostat mode temperature coefficient: 35 ppm/°C Low power consumption: 2.5 μA max @ 2.7 V and 125°C Wide bandwidth: 4 MHz (5 kΩ option) Power-on EEPROM refresh time

文件：448.89 Kbytes 頁數(shù)：24 Pages

AD

亞德諾

絲?。?strong>84；Package：LFCSP_UD；Single-Channel, 128-/64-/32-Position, Up/Down, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer

FEATURES Nominal resistor tolerance error: ±8% maximum Wiper current: ±6 mA Rheostat mode temperature coefficient: 35 ppm/°C Low power consumption: 2.5 μA max @ 2.7 V and 125°C Wide bandwidth: 4 MHz (5 kΩ option) Power-on EEPROM refresh time

文件：448.89 Kbytes 頁數(shù)：24 Pages

AD

亞德諾

絲?。?strong>84；Package：SOT-523；Digital Transistor

Features - Epitaxial planar die construction. - Built-in biasing resistors, R1≠R2. - AEC-Q101 Qualified.

文件：485.13 Kbytes 頁數(shù)：5 Pages

COMCHIP

典琦

絲?。?strong>84；Package：SC-70；40 V, 200 mA Schottky barrier dual diode

1. General description Planar Schottky barrier dual diode with an integrated guard ring for stress protection, encapsulated in a very small SOT323 (SC-70) Surface-Mounted Device (SMD) plastic package. 2. Features and benefits ? Very low forward voltage ? Very low reverse current ? Guard ri

文件：189.23 Kbytes 頁數(shù)：8 Pages

NEXPERIA

安世

絲印：84；Package：SC-70；40 V, 200 mA Schottky barrier dual diode

1. General description Planar Schottky barrier dual diode with an integrated guard ring for stress protection, encapsulated in a very small SOT323 (SC-70) Surface-Mounted Device (SMD) plastic package. 2. Features and benefits ? Very low forward voltage ? Very low reverse current ? Guard ri

文件：188.79 Kbytes 頁數(shù)：8 Pages

NEXPERIA

安世

絲印：84；DIGITAL TRANSISTOR

Features 1) Built-In Biasing Resistors, R1 = R2 = 10kΩ 2) Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors (see inner circuit) . 3) Only the on/off conditions need to be set for operation, making the circuit design e

文件：704.49 Kbytes 頁數(shù)：9 Pages

ROHM

羅姆

絲?。?strong>84；Package：SOT-23；Digital Transistor

Features - Epitaxial planar die construction. - Built-in biasing resistors, R1≠R2.

文件：1.09282 Mbytes 頁數(shù)：5 Pages

COMCHIP

典琦

絲?。?strong>84；Package：EMT3；100mA / 50V Digital transistors (with built-in resistors)

文件：87.48 Kbytes 頁數(shù)：4 Pages

ROHM

羅姆

絲印：84；Package：SMT3；100mA / 50V Digital transistors (with built-in resistors)

文件：87.48 Kbytes 頁數(shù)：4 Pages

ROHM

羅姆

絲?。?strong>84；Package：SOT-723；Digital Transistor

Features - Epitaxial planar die construction. - Built-in biasing resistors, R1≠R2.

文件：482.01 Kbytes 頁數(shù)：5 Pages

COMCHIP

典琦