Clock Switch for ATCA/AMC and PCIe Applications

Features ? Clock switch for PCIe and ATCA/AMC applications ? Supports local and common ATCA/AMC clock modes ? Bi-directional clock I/O FCLK: - When operating as an output, FCLK is a source-terminated HCSL signal. - When operating as an input, FCLK accepts HCSL, LVDS and LVPECL levels. ? Lo

文件：680.27 Kbytes 頁(yè)數(shù)：19 Pages

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Clock Switch for ATCA/AMC and PCIe Applications

文件：484.92 Kbytes 頁(yè)數(shù)：18 Pages

IDT

絲印：31752AIL；Package：TSSOP；Clock Switch for ATCA/AMC and PCIe Applications

Features ? Clock switch for PCIe and ATCA/AMC applications ? Supports local and common ATCA/AMC clock modes ? Bi-directional clock I/O FCLK: - When operating as an output, FCLK is a source-terminated HCSL signal. - When operating as an input, FCLK accepts HCSL, LVDS and LVPECL levels. ? Lo

文件：680.27 Kbytes 頁(yè)數(shù)：19 Pages

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絲?。?a target="_blank" title="Marking" href="/31752ail/marking.html">31752AIL；Package：TSSOP；Clock Switch for ATCA/AMC and PCIe Applications

Features ? Clock switch for PCIe and ATCA/AMC applications ? Supports local and common ATCA/AMC clock modes ? Bi-directional clock I/O FCLK: - When operating as an output, FCLK is a source-terminated HCSL signal. - When operating as an input, FCLK accepts HCSL, LVDS and LVPECL levels. ? Lo

文件：680.27 Kbytes 頁(yè)數(shù)：19 Pages

RENESAS

瑞薩

Clock Switch for ATCA/AMC and PCIe Applications

文件：484.92 Kbytes 頁(yè)數(shù)：18 Pages

IDT

Clock Switch for ATCA/AMC and PCIe Applications

文件：484.92 Kbytes 頁(yè)數(shù)：18 Pages

IDT

Clock Switch for ATCA/AMC and PCIe Applications

文件：484.92 Kbytes 頁(yè)數(shù)：18 Pages

IDT

Clock Switch For ATCA/AMC And PCIe Applications

The 831752I is a high-performance, differential HCSL clock switch. The device is designed for the routing of PCIe clock signals in ATCA/AMC system and is optimized for PCIe Gen 1, Gen 2 and Gen 3. The device has one differential, bi-directional I/O (FCLK) for connection to ATCA clock sources and to ·Clock switch for PCIe and ATCA/AMC applications\n·Supports local and common ATCA/AMC clock modes\n·Bi-directional clock I/O FCLK: -When operating as an output, FCLK is a source-terminated HCSL signal. - When operating as an input, FCLK accepts HCSL, LVDS and LVPECL levels.\n·Local clock input (CLK);

Renesas

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Package：2-SMD，J 形引線；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：電感器，線圈，扼流圈 固定電感器 描述：FIXED IND 2.2UH 16A 6 MOHM SMD

Würth Elektronik

Package：16-TSSOP（0.173"，4.40mm 寬）；包裝：托盤 類別：集成電路（IC） 時(shí)鐘緩沖器，驅(qū)動(dòng)器 描述：NETWORK TIMING

Renesas Electronics America Inc