Low Skew, 1-to-8 Differential/LVCMOS-to- LVCMOS Fanout Buffer

FEATURES ? Eight LVCMOS/LVTTL outputs, (7Ω typical output impedance) ? Selectable LVCMOS_CLK or differential CLK, nCLK inputs ? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? Maximum Output Frequency: 350MHz ? Output Skew: (3.3V± 5): 100

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8:1, Single-Ended Multiplexer

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IDT

絲?。?a target="_blank" title="Marking" href="/83080eibz/marking.html">83080EIBZ；Package：14LdSOIC；?15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers

±15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers The ISL8308xE are BiCMOS, ESD protected, 5V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Each driver output, and receiver input, is protected against ±15kV ESD strik

文件：1.15276 Mbytes 頁數(shù)：21 Pages

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絲?。?a target="_blank" title="Marking" href="/83082eibz/marking.html">83082EIBZ；Package：8LdSOIC；?15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers

±15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers The ISL8308xE are BiCMOS, ESD protected, 5V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Each driver output, and receiver input, is protected against ±15kV ESD strik

文件：1.15276 Mbytes 頁數(shù)：21 Pages

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絲?。?a target="_blank" title="Marking" href="/83083eibz/marking.html">83083EIBZ；Package：14LdSOIC；?15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers

±15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers The ISL8308xE are BiCMOS, ESD protected, 5V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Each driver output, and receiver input, is protected against ±15kV ESD strik

文件：1.15276 Mbytes 頁數(shù)：21 Pages

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絲印：83084EIBZ；Package：8LdSOIC；?15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers

±15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers The ISL8308xE are BiCMOS, ESD protected, 5V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Each driver output, and receiver input, is protected against ±15kV ESD strik

文件：1.15276 Mbytes 頁數(shù)：21 Pages

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絲印：83085EIBZ；Package：8LdSOIC；?15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers

±15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers The ISL8308xE are BiCMOS, ESD protected, 5V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Each driver output, and receiver input, is protected against ±15kV ESD strik

文件：1.15276 Mbytes 頁數(shù)：21 Pages

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絲?。?a target="_blank" title="Marking" href="/83086eibz/marking.html">83086EIBZ；Package：14LdSOIC；?15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers

±15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers The ISL8308xE are BiCMOS, ESD protected, 5V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Each driver output, and receiver input, is protected against ±15kV ESD strik

文件：1.15276 Mbytes 頁數(shù)：21 Pages

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絲?。?a target="_blank" title="Marking" href="/83088eibz/marking.html">83088EIBZ；Package：8LdSOIC；?15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers

±15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers The ISL8308xE are BiCMOS, ESD protected, 5V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Each driver output, and receiver input, is protected against ±15kV ESD strik

文件：1.15276 Mbytes 頁數(shù)：21 Pages

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Low Skew,1-to-8 Differential/LVCMOS-to-LVCMOS Fanout Buffer

The 8308I is a low-skew, 1-to-8 Fanout Buffer. The 8308I has two selectable clock inputs. The CLK, nCLK pair can accept most differential input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/ LVTTL outputs are designed to drive 50? series or parallel termina ? Eight LVCMOS/LVTTL outputs, (7Ω typical output impedance)\n? Selectable LVCMOS_CLK or differential CLK, nCLK inputs\n? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL\n? Maximum Output Frequency: 350MHz\n? Output Skew: (3.3V± 5%): 100ps (maxi;

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