POWER RESET IC

文件：201.95 Kbytes 頁數(shù)：6 Pages

UTC

友順

POWER RESET IC

文件：201.95 Kbytes 頁數(shù)：6 Pages

UTC

友順

POWER RESET IC

文件：201.95 Kbytes 頁數(shù)：6 Pages

UTC

友順

POWER RESET IC

文件：201.95 Kbytes 頁數(shù)：6 Pages

UTC

友順

POWER RESET IC

文件：201.95 Kbytes 頁數(shù)：6 Pages

UTC

友順

POWER RESET IC

文件：201.95 Kbytes 頁數(shù)：6 Pages

UTC

友順

絲印：8130IAZ；Package：20LdQSOP；Advanced Single Universal Pulse-Width Modulation (PWM) Controller

文件：1.62197 Mbytes 頁數(shù)：23 Pages

RENESAS

瑞薩

絲印：8130IRZ；Package：20Ld4x4QFN；Advanced Single Universal Pulse-Width Modulation (PWM) Controller

文件：1.62197 Mbytes 頁數(shù)：23 Pages

RENESAS

瑞薩

Dual VCXO W/3.3V,2.5V LVPECL FemtoClock? PLL

The 813001I is a dual VCXO + FemtoClock? Multiplier designed for use in Discrete PLL loops. Two selectable external VCXO crystals allow the device to be used in multi-rate applications, where a given line card can be switched, for example, between 1Gb Ethernet (125MHz system reference clock) and 1Gb ·One 3.3V or 2.5V LVPECL output pair\n·Two selectable crystal oscillator interfaces for the VCXO, one differential clock or one LVCMOS/LVTTL clock inputs\n·CLK1/nCLK1 supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL\n·Crystal operating frequency range: 14MHz - 24MHz\n·VCO range: ;

Renesas

瑞薩

Frequency Generator/Jitter Attenuation Device For Wireless Infrastructure Applications

The 813076I is a member of the family of high performance clock solutions from IDT. The 813076I a PLL based synchronous clock solution that is optimized for wireless infrastructure equipment where frequency translation and jitter attenuation is needed.\n\nThe device contains two internal PLL stages Two operation modes: input frequency multiplier and VCXO\nNine differential LVPECL outputs, organized in three independent output banks\nTwo selectable differential input clocks can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL\nMaximum output frequency: 614.4MHz\n;

Renesas

瑞薩