Presettable synchronous 4-bit binary up/down counter

GENERAL DESCRIPTION The 74HC/HCT191 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT191 are asynchronously presettable 4-bit binary up/down counters. They contain four master/

文件：108.17 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Presettable synchronous 4-bit binary up/down counter

1. General description The 74HC191 is an asynchronously presettable 4-bit binary up/down counter. It contains four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation. Asynchronous parallel load capabil

文件：296.75 Kbytes 頁數(shù)：18 Pages

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Presettable synchronous 4-bit binary up/down counter

1. General description The 74HC191 is an asynchronously presettable 4-bit binary up/down counter. It contains four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation. Asynchronous parallel load capabil

文件：296.75 Kbytes 頁數(shù)：18 Pages

NEXPERIA

安世

Presettable synchronous 4-bit binary up/down counter

GENERAL DESCRIPTION The 74HC/HCT191 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT191 are asynchronously presettable 4-bit binary up/down counters. They contain four master/

文件：108.17 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Presettable synchronous 4-bit binary up/down counter

GENERAL DESCRIPTION The 74HC/HCT191 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT191 are asynchronously presettable 4-bit binary up/down counters. They contain four master/

文件：108.17 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Presettable synchronous 4-bit binary up/down counter

GENERAL DESCRIPTION The 74HC/HCT191 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT191 are asynchronously presettable 4-bit binary up/down counters. They contain four master/

文件：108.17 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Presettable synchronous 4-bit binary up/down counter

GENERAL DESCRIPTION The 74HC/HCT191 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT191 are asynchronously presettable 4-bit binary up/down counters. They contain four master/

文件：108.17 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Presettable synchronous 4-bit binary up/down counter

1. General description The 74HC191 is an asynchronously presettable 4-bit binary up/down counter. It contains four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation. Asynchronous parallel load capabil

文件：296.75 Kbytes 頁數(shù)：18 Pages

NEXPERIA

安世

Presettable synchronous 4-bit binary up/down counter

The 74HC191 is an asynchronously presettable 4-bit binary up/down counter. It contains four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation. Asynchronous parallel load capability permits the counter to b ? Complies with JEDEC standard no. 7A\n? CMOS input levels\n? Synchronous reversible counting\n? Asynchronous parallel load\n? Count enable control for synchronous expansion\n? Single up/down control input\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? Spe;

Nexperia

安世

Presettable synchronous 4-bit binary up/down counter

The 74HC191 is an asynchronously presettable 4-bit binary up/down counter. It contains four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation. Asynchronous parallel load capability permits the counter to b ? Complies with JEDEC standard no. 7A\n? CMOS input levels\n? Synchronous reversible counting\n? Asynchronous parallel load\n? Count enable control for synchronous expansion\n? Single up/down control input\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? Spe;

Nexperia

安世