Quad D-type flip-flop; positive-edge trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (

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Quad D-type flip-flop; positive-edge trigger; 3-state

1. General description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their co

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Quad D-type flip-flop; positive-edge trigger; 3-state

The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that m ? Complies with JEDEC standard no. 7A\n? Input levels:? For 74HC173: CMOS level\n? For 74HCT173: TTL level\n\n? Gated input enable for hold (do nothing) mode\n? Gated output enable control mode\n? Edge-triggered D-type register\n? Asynchronous master reset\n? ESD protection:? HBM JESD22-A114F exceed;

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74HC173DB - Quad D-type flip-flop; positive-edge trigger; 3-state

Quad D-type flip-flop; positive-edge trigger; 3-state - The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will ·Complies with JEDEC standard no. 7A\n·Input levels:·For 74HC173: CMOS level\n·For 74HCT173: TTL level;

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Quad D-type flip-flop; positive-edge trigger; 3-state

The 74HC173-Q100; 74HCT173-Q100 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inp

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Package：16-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：主復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 4BIT 16SO

Nexperia USA Inc.

Package：16-SSOP（0.209"，5.30mm 寬）；包裝：管件 功能：主復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 4BIT 16SSOP

Nexperia USA Inc.

Package：16-SSOP（0.209"，5.30mm 寬）；包裝：管件 功能：主復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 4BIT 16SSOP

Nexperia USA Inc.