Transceivers/registers

DESCRIPTION The 74F651A and 74F652A transceivers/registers consist of bus transceiver circuits with 3–State outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked

文件：168.44 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Transceivers/Registers

文件：188.34 Kbytes 頁數(shù)：10 Pages

NSC

國半

Transceivers/Registers

General Description These devices consist of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate cl

文件：73.97 Kbytes 頁數(shù)：8 Pages

FAIRCHILD

仙童半導(dǎo)體

Transceivers/Registers

General Description These devices consist of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate cl

文件：71.67 Kbytes 頁數(shù)：8 Pages

FAIRCHILD

仙童半導(dǎo)體