Octal transceiver/register, non-inverting 3-State

DESCRIPTION The 74F646/74F646A and 74F648/74F648A transceivers/registers consist of bus transceiver circuits with 3–state outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus

文件：121.1 Kbytes 頁數(shù)：16 Pages

PHI

PHI

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes 頁數(shù)：12 Pages

NSC

國半

Octal transceiver/register, non-inverting (3-State)

DESCRIPTION\nThe 74F646/74F646A and 74F648/74F648A transceivers/registers consist of bus transceiver circuits with 3–state outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus wil ? Combines 74F245 and two 74F374 type functions in one chip\n? High impedance base inputs for reduced loading (70μA in high and low states)\n? Independent registers for A and B buses\n? Multiplexed real-time and stored data\n? Choice of non-inverting and inverting data paths\n? Controlled ramp outpu;

恩XP

Octal transceiver/register, non-inverting 3-State

DESCRIPTION The 74F646/74F646A and 74F648/74F648A transceivers/registers consist of bus transceiver circuits with 3–state outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus

文件：121.1 Kbytes 頁數(shù)：16 Pages

PHI

PHI

Octal Transceiver/Register with 3-STATE Outputs

General Description These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the a

文件：78.37 Kbytes 頁數(shù)：9 Pages

FAIRCHILD

仙童半導(dǎo)體

Octal Transceiver/Register with 3-STATE Outputs

General Description These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the a

文件：78.37 Kbytes 頁數(shù)：9 Pages

FAIRCHILD

仙童半導(dǎo)體

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes 頁數(shù)：12 Pages

NSC

國半

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes 頁數(shù)：12 Pages

NSC

國半

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes 頁數(shù)：12 Pages

NSC

國半

Octal Transceiver/Register with TRI-STATE Outputs

文件：216.07 Kbytes 頁數(shù)：12 Pages

NSC

國半