Octal Bus Transceiver with 3-STATE Outputs

General Description These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA, have 3- STATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive (T

文件：54.69 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導體

Package：20-DIP（0.300"，7.62mm）；包裝：管件 類別：集成電路（IC） 緩沖器，驅(qū)動器，接收器，收發(fā)器 描述：IC TRANSCEIVER INVERT 5.5V 20DIP

ONSEMI

安森美半導體

Octal Bus Transceiver with 3-STATE Outputs

General Description These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA, have 3- STATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive (T

文件：54.69 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導體

OCTAL BUS TRANSCEIVER, INVERTING WITH 3-STATE OUTPUTS

The MC74F640 is an octal transceiver featuring inverting 3-state bus compatible outputs in both transmit and receive directions. The B port outputs are capable of sinking 64 mA and sourcing 15 mA, providing very good capacitive drive characteristics. ? High-Impedance NPN Base Inputs for Redu

文件：88.25 Kbytes 頁數(shù)：4 Pages

MOTOROLA

摩托羅拉

Octal bus transceiver, inverting 3-State

DESCRIPTION The 74F640 is an octal transceiver featuring inverting 3-State bus compatible outputs in both transmit and receive directions. The B port outputs are capable of sinking 64mA and sourcing 15mA, providing very good capacitive drive characteristics. The device features an Output Enable

文件：85.16 Kbytes 頁數(shù)：11 Pages

PHI

PHI