Octal D flip-flop

DESCRIPTION The 74F273 has eight edge–triggered D–type flip–flops with individual D inputs and Q outputs. FEATURES ? High impedance inputs for reduced loading (20μA in Low and High states) ? Ideal buffer for MOS microprocessor or memory ? Eight edge–triggered D–type flip–flops ? Buffere

文件：79.98 Kbytes 頁數(shù)：10 Pages

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PHI

Octal D flip??lop

DESCRIPTION The 74F273 has eight edge–triggered D–type flip–flops with individual D inputs and Q outputs. FEATURES ? High impedance inputs for reduced loading (20μA in Low and High states) ? Ideal buffer for MOS microprocessor or memory ? Eight edge–triggered D–type flip–flops ? Buffere

文件：96.04 Kbytes 頁數(shù)：10 Pages

PHI

PHI

Octal D flip-flop

DESCRIPTION The 74F273 has eight edge–triggered D–type flip–flops with individual D inputs and Q outputs. FEATURES ? High impedance inputs for reduced loading (20μA in Low and High states) ? Ideal buffer for MOS microprocessor or memory ? Eight edge–triggered D–type flip–flops ? Buffere

文件：79.98 Kbytes 頁數(shù)：10 Pages

PHI

PHI

Octal D flip-flop

DESCRIPTION The 74F273 has eight edge–triggered D–type flip–flops with individual D inputs and Q outputs. FEATURES ? High impedance inputs for reduced loading (20μA in Low and High states) ? Ideal buffer for MOS microprocessor or memory ? Eight edge–triggered D–type flip–flops ? Buffere

文件：79.98 Kbytes 頁數(shù)：10 Pages

PHI

PHI

Octal D flip-flop

DESCRIPTION\nThe 74F273 has eight edge–triggered D–type flip–flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip–flops\nsimultaneously.FEATURES\n?High impedance inputs for reduced loading (20μA in Low and High stat ?High impedance inputs for reduced loading (20μA in Low and High states)\n?Ideal buffer for MOS microprocessor or memory\n?Eight edge–triggered D–type flip–flops\n?Buffered common clock\n?Buffered asynchronous Master Reset\n?See 74F377A for clock enable version\n?See 74F373 for transparent latch ver;

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Octal D flip-flop

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