64-bit TTL bipolar RAM, inverting 3-State

DESCRIPTION The 74F189A is a high speed, 64-bit RAM organized as a 16-word by 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on chip. The outputs are in high impedance state whenever the chip enable (CE) is high. The outputs are active only in the READ mode (

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PHI

PHI

64-bit TTL bipolar RAM, inverting (3-State)

DESCRIPTION\nThe 74F189A is a high speed, 64-bit RAM organized as a 16-word by 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on chip. The outputs are in high impedance state whenever the chip enable (CE) is high. The outputs are active only in the READ mode (WE= ?High speed performance\n?Address access time: 8ns max vs 28ns for 74F189\n?Schottky clamp TTL\n?Inverting outputs (for non-inverting outputs see 74F219A)\n?74F189A in 150 mil wide SO is preferred options for new designs;

恩XP

64-Bit Random Access Memory with TRI-STATEE Outputs

文件：166.99 Kbytes 頁數(shù)：8 Pages

NSC

國半

64-Bit Random Access Memory with 3-STATE Outputs

General Description The F189 is a high-speed 64-bit RAM organized as a 16-word by 4-bit array. Address inputs are buffered to mini mize loading and are fully decoded on-chip. The outputs are 3-STATE and are in the high impedance state when ever the Chip Select (CS) input is HIGH. The outp

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FAIRCHILD

仙童半導(dǎo)體

64-Bit Random Access Memory with TRI-STATEE Outputs

文件：166.99 Kbytes 頁數(shù)：8 Pages

NSC

國半