Quad D flip-flop

DESCRIPTION The 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. FEATURES ? Four edge-triggered D-type flip-flops ? B

文件：82.25 Kbytes 頁數(shù)：10 Pages

PHI

PHI

Quad D flip-flop

DESCRIPTION The 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. FEATURES ? Four edge-triggered D-type flip-flops ? B

文件：82.25 Kbytes 頁數(shù)：10 Pages

PHI

PHI

Quad D-Type Flip-Flop

General Description The 74F175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each fli

文件：80.45 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

Quad D-Type Flip-Flop

General Description The 74F175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each fli

文件：80.45 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體