Quad D-Type Flip-Flop

General Description The 74F175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each fli

文件：80.45 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導體

Quad D flip-flop

DESCRIPTION\nThe 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, on ? Four edge-triggered D-type flip-flops\n? Buffered common clock\n? Buffered asynchronous Master Reset\n? True and complementary outputs\n? Industrial temperature range available (–40°C to +85°C)\n? PNP light loading inputs;

恩XP

Quad D flip-flop

恩XP

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：管件 功能：主復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 4BIT 16SOIC

ONSEMI

安森美半導體

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：管件 功能：主復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 4BIT 16SOIC

ONSEMI

安森美半導體

Package：16-SOIC（0.209"，5.30mm 寬）；包裝：卷帶（TR） 功能：主復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 4BIT 16SOP

ONSEMI

安森美半導體