Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Trig gering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inp

文件：55.22 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

Dual J-K negative edge-triggered flip-flop with common clock and reset

DESCRIPTION The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with common clock and reset inputs, features individual J, K, Clock (CP), Set (SD) and Reset (RD) inputs, true and complementary outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table

文件：51.33 Kbytes 頁數(shù)：6 Pages

PHI

PHI

Dual J-K negative edge-triggered flip-flop with common clock and reset

DESCRIPTION\nThe 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with common clock and reset inputs, features individual J, K, Clock (CP), Set (SD) and Reset (RD) inputs, true and complementary outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table re

恩XP

Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

ONSEMI

安森美半導(dǎo)體

Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Trig gering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inp

文件：55.22 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Trig gering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inp

文件：55.22 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

Package：14-DIP（0.300"，7.62mm）；包裝：袋 功能：設(shè)置（預(yù)設(shè)）和復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF JK TYPE DUAL 1BIT 14DIP

ONSEMI

安森美半導(dǎo)體