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74ACT16657DLR集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器規(guī)格書PDF中文資料
| 廠商型號 |
74ACT16657DLR |
| 參數(shù)屬性 | 74ACT16657DLR 封裝/外殼為56-BSSOP（0.295"，7.50mm 寬）；包裝為卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶；類別為集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器；產(chǎn)品描述：IC TXRX NON-INVERT 5.5V 56SSOP |
| 功能描述 | 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS |
| 絲印標(biāo)識 | |
| 封裝外殼 | SSOP / 56-BSSOP（0.295"，7.50mm 寬） |
| 文件大小 |
547.54 Kbytes |
| 頁面數(shù)量 |
11 頁 |
| 生產(chǎn)廠商 | TI |
| 中文名稱 | 德州儀器 |
| 網(wǎng)址 | |
| 數(shù)據(jù)手冊 | |
| 更新時間 | 2026-1-19 13:13:00 |
| 人工找貨 | 74ACT16657DLR價格和庫存，歡迎聯(lián)系客服免費人工找貨 |
74ACT16657DLR規(guī)格書詳情
74ACT16657DLR屬于集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器。由德州儀器制造生產(chǎn)的74ACT16657DLR緩沖器，驅(qū)動器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動器、接收器和收發(fā)器允許隔離對某個電路的邏輯信號的訪問，以用于另一電路。緩沖器將其輸入信號（不變或反相）傳遞到其輸出，并可能用于清除弱信號或驅(qū)動負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進行隔離通信。
Members of the Texas Instruments
WidebusE Family
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPICE (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’ACT16657 contain two noninverting octal
transceiver sections with separate parity
generator/checker circuits and control signals.
For either section, the transmit/receive (1T/R or
2T/R) input determines the direction of data flow.
When 1T/R (or 2T/R) is high, data flows from the
1A (or 2A) port to the 1B (or 2B) port (transmit
mode); when 1T/R (or 2T/R) is low, data flows
from the 1B (or 2B) port to the 1A (or 2A) port
(receive mode). When the output-enable (1OE or
2OE) input is high, both the 1A (or 2A) and 1B (or
2B) ports are in the high-impedance state.
Odd or even parity is selected by a logic high or
low level, respectively, on the 1ODD/EVEN (or
2ODD/EVEN) input. 1PARITY (or 2PARITY)
carries the parity bit value; it is an output from the
parity generator/checker in the transmit mode and
an input to the parity generator/checker in the
receive mode.
In the transmit mode, after the 1A (or 2A) bus is polled to determine the number of high bits, 1PARITY (or
2PARITY) is set to the logic level that maintains the parity sense selected by the level at the 1ODD/EVEN (or
2ODD/EVEN) input. For example, if 1ODD/EVEN is low (even parity selected) and there are five high bits on
the 1A bus, then 1PARITY is set to the logic high level so that an even number of the nine total bits (eight 1A-bus
bits plus parity bit) are high.
產(chǎn)品屬性
更多- 產(chǎn)品編號：
74ACT16657DLR
- 制造商：
Texas Instruments
- 類別：
集成電路（IC） > 緩沖器，驅(qū)動器，接收器，收發(fā)器
- 系列：
74ACT
- 包裝：
卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶
- 邏輯類型：
收發(fā)器，非反相
- 每個元件位數(shù)：
8
- 輸出類型：
三態(tài)
- 電流 - 輸出高、低：
24mA，24mA
- 電壓 - 供電：
4.5V ~ 5.5V
- 工作溫度：
-40°C ~ 85°C（TA）
- 安裝類型：
表面貼裝型
- 封裝/外殼：
56-BSSOP（0.295"，7.50mm 寬）
- 供應(yīng)商器件封裝：
56-SSOP
- 描述：
IC TXRX NON-INVERT 5.5V 56SSOP
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
TI(德州儀器) |
2021+ |
SSOP-56 |
499 |
詢價 | |||
Texas Instruments |
24+25+ |
16500 |
全新原廠原裝現(xiàn)貨!受權(quán)代理!可送樣可提供技術(shù)支持! |
詢價 | |||
TI/德州儀器 |
25+ |
原廠封裝 |
10280 |
詢價 | |||
TI |
25+ |
SSOP-56-300mil |
21000 |
原裝正品現(xiàn)貨,原廠訂貨,可支持含稅原型號開票。 |
詢價 | ||
HITACHI |
23+ |
SOP |
5000 |
原廠授權(quán)代理,海外優(yōu)勢訂貨渠道?？商峁┐罅繋齑?詳 |
詢價 | ||
24+ |
N/A |
65000 |
一級代理-主營優(yōu)勢-實惠價格-不悔選擇 |
詢價 | |||
TI/德州儀器 |
23+ |
SSOP56 |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價 | ||
TEXASINSTRU |
23+ |
SSOL |
9856 |
原裝正品,假一罰百! |
詢價 | ||
TexasInstruments |
18+ |
IC16BITTXRX56-SSOP |
6580 |
公司原裝現(xiàn)貨/歡迎來電咨詢! |
詢價 | ||
TI |
24+ |
40 |
詢價 |
