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          型號(hào)下載 訂購(gòu)功能描述制造商 上傳企業(yè)LOGO
          
                    
          74ACT11245
          OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
          
3-State Outputs Drive Bus Lines Directly
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at

          文件：893.33 Kbytes 頁(yè)數(shù)：24 Pages
          TI
          德州儀器
          

          74ACT11245
          OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
          文件：107.84 Kbytes 頁(yè)數(shù)：6 Pages
          TI
          德州儀器
          

          74ACT11245
          OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
          文件：1.34287 Mbytes 頁(yè)數(shù)：25 Pages
          TI
          德州儀器
          

          74ACT11245
          具有三態(tài)輸出的八路總線收發(fā)器
          The octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.\nThe device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level a  ? 3-State Outputs Drive Bus Lines Directly? Inputs Are TTL-Voltage Compatible? Flow-Through Architecture Optimizes PCB Layout? Center-Pin VCC and GND Configurations MinimizeHigh-Speed Switching Noise? EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process? 500-mA Typical Latch-Up Immunity at 125°C;
          TI
          德州儀器
          

          74ACT11245DBLE
          OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
          
3-State Outputs Drive Bus Lines Directly
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at

          文件：893.33 Kbytes 頁(yè)數(shù)：24 Pages
          TI
          德州儀器
          

          74ACT11245DBR
          OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
          
3-State Outputs Drive Bus Lines Directly
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at

          文件：893.33 Kbytes 頁(yè)數(shù)：24 Pages
          TI
          德州儀器
          

          74ACT11245DBRE4
          OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
          
3-State Outputs Drive Bus Lines Directly
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at

          文件：893.33 Kbytes 頁(yè)數(shù)：24 Pages
          TI
          德州儀器
          

          74ACT11245DBRG4
          OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
          
3-State Outputs Drive Bus Lines Directly
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at

          文件：893.33 Kbytes 頁(yè)數(shù)：24 Pages
          TI
          德州儀器
          

          74ACT11245DW
          絲?。?a target="_blank" title="Marking" href="/act11245/marking.html">ACT11245；Package：SOIC；OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
          
3-State Outputs Drive Bus Lines Directly
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at

          文件：893.33 Kbytes 頁(yè)數(shù)：24 Pages
          TI
          德州儀器
          

          74ACT11245DWE4
          OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
          
3-State Outputs Drive Bus Lines Directly
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at

          文件：893.33 Kbytes 頁(yè)數(shù)：24 Pages
          TI
          德州儀器
          

          
            
          
		
        
          
            
          
                
          技術(shù)參數(shù)
          
            
          
            
            
            	
          • VCC(Min)(V)：
            4.5
          • VCC(Max)(V)：
            5.5
          • Bits(#)：
            8
          • Voltage(Nom)(V)：
            5
          • F @ nom voltage(Max)(MHz)：
            90
          • ICC @ nom voltage(Max)(mA)：
            0.08
          • tpd @ nom Voltage(Max)(ns)：
            10
          • IOL(Max)(mA)：
            24
          • IOH(Max)(mA)：
            -24
          • Rating：
            Catalog
          • Operating temperature range(C)：
            -40 to 85
          
            
          
        
          
            
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