3.3V CMOS 16-BIT TRANSPARENT LATCH

FEATURES: ? 0.5 MICRON CMOS Technology ? Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) ? VCC = 3.3V ± 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended Range ? CMOS power levels (0.4μ W typ. static) ? Rail-to

文件：239.37 Kbytes 頁數(shù)：8 Pages

RENESAS

瑞薩

3.3V CMOS 16-BIT TRANSPARENT LATCH

FEATURES: ? 0.5 MICRON CMOS Technology ? Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) ? VCC = 3.3V ± 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended Range ? CMOS power levels (0.4μ W typ. static) ? Rail-to

文件：239.37 Kbytes 頁數(shù)：8 Pages

RENESAS

瑞薩

8 BIT SIPO SHIFT REGISTER

Description The M54HCxxx and M54HCTxxx series are composed of over 90 types of high speed CMOS functions specifically designed to meet the radiation requirements of the aerospace industry. It includes a large set of gates, Flip-Flops, Multiplexers, Counters, Bus interface and several other functi

文件：254.99 Kbytes 頁數(shù)：12 Pages

STMICROELECTRONICS

意法半導(dǎo)體

SYNCHRONOUS DECADE RATE MULTIPLIER

DESCRIPTION 一 The 167 contains asynchronous decade counter and four decoding gates that serve to gate the clock through to the output at a sub- multiple of the clock frequency. The output pulse rate, relative to the clock frequency, is determined by signals applied to the Select (So 一 Ss) input

文件：297.73 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

SYNCHRONOUS DECADE RATE MULTIPLIER

DESCRIPTION 一 The 167 contains asynchronous decade counter and four decoding gates that serve to gate the clock through to the output at a sub- multiple of the clock frequency. The output pulse rate, relative to the clock frequency, is determined by signals applied to the Select (So 一 Ss) input

文件：297.73 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

SYNCHRONOUS DECADE RATE MULTIPLIER

DESCRIPTION 一 The 167 contains asynchronous decade counter and four decoding gates that serve to gate the clock through to the output at a sub- multiple of the clock frequency. The output pulse rate, relative to the clock frequency, is determined by signals applied to the Select (So 一 Ss) input

文件：297.73 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

SYNCHRONOUS DECADE RATE MULTIPLIER

DESCRIPTION 一 The 167 contains asynchronous decade counter and four decoding gates that serve to gate the clock through to the output at a sub- multiple of the clock frequency. The output pulse rate, relative to the clock frequency, is determined by signals applied to the Select (So 一 Ss) input

文件：297.73 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS

The SN54 /74LS168 and SN54 /74LS169 are fully synchronous 4-stage up/down counters featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. The SN54 /74LS168 counts in a BCD decade (8, 4, 2, 1) sequence, whil

文件：272.36 Kbytes 頁數(shù)：8 Pages

MOTOROLA

摩托羅拉

MachFlex?, 171G C #18 Str BC, PVC-NYL Ins, OA TC Brd, TPE Jkt, 1000V WTTC, 600V TC-ER

Product Description MachFlex? for High Flex, 17+1G Conductor 18AWG (16x30) Bare Copper, PVC-NYL Insulation, Overall Tinned Copper Braid(85%) Shield, TPE Outer Jacket, 1000V WTTC, 600V TC-ER

文件：170.59 Kbytes 頁數(shù)：3 Pages

BELDEN

百通

MachFlex?, 171G C #18 Str BC, PVC-NYL Ins, OA TC Brd, TPE Jkt, 1000V WTTC, 600V TC-ER

Product Description MachFlex? for High Flex, 17+1G Conductor 18AWG (16x30) Bare Copper, PVC-NYL Insulation, Overall Tinned Copper Braid(85%) Shield, TPE Outer Jacket, 1000V WTTC, 600V TC-ER

文件：170.59 Kbytes 頁數(shù)：3 Pages

BELDEN

百通