CMOS SyncBiFIFOTM 64 x 36 x 2

? Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) ? Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions ? Mailbox bypass Register for each FIFO ? Progra

文件：611.36 Kbytes 頁(yè)數(shù)：26 Pages

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CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

? Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) ? 64 x 36 storage capacity FIFO buffering data from Port A to Port B ? Mailbox bypass registers in each direction ? Dynamic Port B bus sizing of 36 bits (l

文件：591.66 Kbytes 頁(yè)數(shù)：27 Pages

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瑞薩

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

? Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) ? 64 x 36 storage capacity FIFO buffering data from Port A to Port B ? Mailbox bypass registers in each direction ? Dynamic Port B bus sizing of 36 bits (l

文件：591.66 Kbytes 頁(yè)數(shù)：27 Pages

RENESAS

瑞薩

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

? Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) ? 64 x 36 storage capacity FIFO buffering data from Port A to Port B ? Mailbox bypass registers in each direction ? Dynamic Port B bus sizing of 36 bits (l

文件：591.66 Kbytes 頁(yè)數(shù)：27 Pages

RENESAS

瑞薩

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

? Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) ? 64 x 36 storage capacity FIFO buffering data from Port A to Port B ? Mailbox bypass registers in each direction ? Dynamic Port B bus sizing of 36 bits (l

文件：591.66 Kbytes 頁(yè)數(shù)：27 Pages

RENESAS

瑞薩

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

? Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) ? 64 x 36 storage capacity FIFO buffering data from Port A to Port B ? Mailbox bypass registers in each direction ? Dynamic Port B bus sizing of 36 bits (l

文件：591.66 Kbytes 頁(yè)數(shù)：27 Pages

RENESAS

瑞薩

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

? Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) ? 64 x 36 storage capacity FIFO buffering data from Port A to Port B ? Mailbox bypass registers in each direction ? Dynamic Port B bus sizing of 36 bits (l

文件：591.66 Kbytes 頁(yè)數(shù)：27 Pages

RENESAS

瑞薩

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

? Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) ? 64 x 36 storage capacity FIFO buffering data from Port A to Port B ? Mailbox bypass registers in each direction ? Dynamic Port B bus sizing of 36 bits (l

文件：591.66 Kbytes 頁(yè)數(shù)：27 Pages

RENESAS

瑞薩

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

? Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) ? 64 x 36 storage capacity FIFO buffering data from Port A to Port B ? Mailbox bypass registers in each direction ? Dynamic Port B bus sizing of 36 bits (l

文件：591.66 Kbytes 頁(yè)數(shù)：27 Pages

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瑞薩

CMOS TRIPLE BUS SyncFIFO? WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

? Two independent FIFOs (64 X 36 storage capacity each) buffer data between bidirectional 36-bit port A and two unidirectional 18/9-bit ports (Port B transmits, Port C receives) ? Clock frequencies up to 67 MHz (10 ns access time) Free-running clock lines for each port: CLKA, CLKB and CLKC, m

文件：570.92 Kbytes 頁(yè)數(shù)：27 Pages

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