Package：16-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 時(shí)鐘發(fā)生器，PLL，頻率合成器 描述：IC PLL BUILDING BLOCK 16-SOIC

Renesas Electronics America Inc

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：管件 類別：集成電路（IC） 時(shí)鐘發(fā)生器，PLL，頻率合成器 描述：IC PLL BUILDING BLOCK 16-SOIC

Renesas Electronics America Inc

PLL Building Block

Description The ICS673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer is a divide by two of

文件：73.87 Kbytes 頁數(shù)：9 Pages

ICST

PLL Building Block

Description The ICS673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer is a divide by two of

文件：73.87 Kbytes 頁數(shù)：9 Pages

ICST

PLL Building Block

Description The ICS673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer is a divide by two of

文件：73.87 Kbytes 頁數(shù)：9 Pages

ICST