絲?。?strong>650R-01LF；Package：SSOP；SYSTEM PERIPHERAL CLOCK SOURCE

Features ? Packaged in 20-pin SSOP (QSOP) ? Pb (lead) free package ? Operating voltage of 3.3 V or 5 V ? Less than one ppm synthesis error in all clocks ? Inexpensive 14.31818 MHz crystal or clock input ? Provides Ethernet and Fast Ethernet clocks ? Provides SCSI clocks ? Provides PCI cloc

文件：382.78 Kbytes 頁數(shù)：9 Pages

RENESAS

瑞薩

絲?。?strong>650R-01LF；Package：SSOP；SYSTEM PERIPHERAL CLOCK SOURCE

Features ? Packaged in 20-pin SSOP (QSOP) ? Pb (lead) free package ? Operating voltage of 3.3 V or 5 V ? Less than one ppm synthesis error in all clocks ? Inexpensive 14.31818 MHz crystal or clock input ? Provides Ethernet and Fast Ethernet clocks ? Provides SCSI clocks ? Provides PCI cloc

文件：382.78 Kbytes 頁數(shù)：9 Pages

RENESAS

瑞薩

Package：20-SSOP（0.154"，3.90mm 寬）；包裝：管件 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC CLK SYNTHESIZER 20-SSOP

Renesas Electronics America Inc

System Peripheral Clock Source

Description The ICS650-01 is a low cost, low jitter, high performance clock synthesizer for system peripheral applications. Using analog/digital Phase-Locked Loop (PLL) techniques, the device accepts a parallel resonant 14.31818 MHz crystal input to produce up to eight output clocks. Featu

文件：42.07 Kbytes 頁數(shù)：4 Pages

ICST

System Peripheral Clock Source

Description The ICS650-01B is a low cost, low jitter, high performance clock synthesizer for system peripheral applications. Using analog/digital Phase-Locked Loop (PLL) techniques, the device accepts a parallel resonant 14.31818 MHz crystal input to produce up to eight output clocks. The

文件：44.92 Kbytes 頁數(shù)：4 Pages

ICST

System Peripheral Clock Source

Description The ICS650-01 is a low cost, low jitter, high performance clock synthesizer for system peripheral applications. Using analog/digital Phase-Locked Loop (PLL) techniques, the device accepts a parallel resonant 14.31818 MHz crystal input to produce up to eight output clocks. Featu

文件：42.07 Kbytes 頁數(shù)：4 Pages

ICST