絲印：601；WE-PD2 SMT Power Inductor

General Properties: It is recommended that the temperature of the component does not exceed +125 °C under worst case conditions Ambient Temperature (referring to IR) -40 up to +85 °C Operating Temperature -40 up to +125 °C Storage Conditions (in original packaging)

文件：660.55 Kbytes 頁數(shù)：6 Pages

WURTHWurth Elektronik GmbH & Co. KG, Germany.

伍爾特伍爾特集團

絲印：601；Package：SOT23-6；100V Dual N-Channel Enhancement Mode MOSFET

Application - Power switch - DC/DC converters

文件：3.4736 Mbytes 頁數(shù)：6 Pages

TECHPUBLIC

臺舟電子

絲?。?strong>601；Package：5-PinSC70；1MHz, 80關(guān)A, RRIO, Op Amps

文件：944.57 Kbytes 頁數(shù)：17 Pages

3PEAK

思瑞浦

絲?。?strong>601；Package：5-PinSOT23；1MHz, 80關(guān)A, RRIO, Op Amps

文件：944.57 Kbytes 頁數(shù)：17 Pages

3PEAK

思瑞浦

絲?。?a target="_blank" title="Marking" href="/601g01il/marking.html">601G01IL；Package：TSSOP；LOW PHASE NOISE CLOCK MULTIPLIER

Description The ICS601-01 is a low-cost, low phase noise, high-performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT’s lowest phase noise multiplier, and also the lowest CMOS part in the industry. Using IDT’s patented analog and digital Phase-Locke

文件：230.01 Kbytes 頁數(shù)：9 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/601g01il/marking.html">601G01IL；Package：TSSOP；LOW PHASE NOISE CLOCK MULTIPLIER

Features ? Packaged in 16-pin SOIC or TSSOP ? Pb (lead) free package ? Uses fundamental 10 - 27 MHz crystal or clock ? Patented PLL with the lowest phase noise ? Output clocks up to 156 MHz at 3.3 V ? Low phase noise: -132 dBc/Hz at 10 kHz ? Low jitter - 18 ps one sigma typ. ? Full swing C

文件：415.35 Kbytes 頁數(shù)：10 Pages

RENESAS

瑞薩

絲?。?a target="_blank" title="Marking" href="/601g01il/marking.html">601G01IL；Package：TSSOP；LOW PHASE NOISE CLOCK MULTIPLIER

Features ? Packaged in 16-pin SOIC or TSSOP ? Pb (lead) free package ? Uses fundamental 10 - 27 MHz crystal or clock ? Patented PLL with the lowest phase noise ? Output clocks up to 156 MHz at 3.3 V ? Low phase noise: -132 dBc/Hz at 10 kHz ? Low jitter - 18 ps one sigma typ. ? Full swing C

文件：415.35 Kbytes 頁數(shù)：10 Pages

RENESAS

瑞薩

絲?。?a target="_blank" title="Marking" href="/601g01il/marking.html">601G01IL；Package：TSSOP；LOW PHASE NOISE CLOCK MULTIPLIER

Description The ICS601-01 is a low-cost, low phase noise, high-performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT’s lowest phase noise multiplier, and also the lowest CMOS part in the industry. Using IDT’s patented analog and digital Phase-Locke

文件：230.01 Kbytes 頁數(shù)：9 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/601g01lf/marking.html">601G01LF；Package：TSSOP；LOW PHASE NOISE CLOCK MULTIPLIER

Description The ICS601-01 is a low-cost, low phase noise, high-performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT’s lowest phase noise multiplier, and also the lowest CMOS part in the industry. Using IDT’s patented analog and digital Phase-Locke

文件：230.01 Kbytes 頁數(shù)：9 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/601g01lf/marking.html">601G01LF；Package：TSSOP；LOW PHASE NOISE CLOCK MULTIPLIER

Features ? Packaged in 16-pin SOIC or TSSOP ? Pb (lead) free package ? Uses fundamental 10 - 27 MHz crystal or clock ? Patented PLL with the lowest phase noise ? Output clocks up to 156 MHz at 3.3 V ? Low phase noise: -132 dBc/Hz at 10 kHz ? Low jitter - 18 ps one sigma typ. ? Full swing C

文件：415.35 Kbytes 頁數(shù)：10 Pages

RENESAS

瑞薩