Triple 3-Input NAND Gates

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NSC

國半

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

General Description\nThis device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition tim ■ Alternate Military/Aerospace device (54LS109) is available. Contact a National Semiconductor Sales Office/Distributor for specifications;

TI

德州儀器

雙J-K觸發(fā)器（帶預(yù)置和清零）

TS871

天水天光