Hex D Flip-Flop with Master Reset

文件：166.34 Kbytes 頁數(shù)：8 Pages

NSC

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Hex D Flip-Flop with Master Reset

General Description\nThe ’F174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-f ■ Edge-triggered D-type inputs\n■ Buffered positive edge-triggered clock\n■ Asynchronous common reset\n■ Guaranteed 4000V minimum ESD protection?;

TI

德州儀器

Hex D Flip-Flop with Master Reset

文件：166.34 Kbytes 頁數(shù)：8 Pages

NSC

國半

Hex D Flip-Flop with Master Reset

文件：166.34 Kbytes 頁數(shù)：8 Pages

NSC

國半

Hex D Flip-Flop with Master Reset

文件：166.34 Kbytes 頁數(shù)：8 Pages

NSC

國半