8-INPUT POSITIVE-NAND GATES

Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Sm

文件：172.22 Kbytes 頁數(shù)：8 Pages

TI

德州儀器

Rad-hard advanced high-speed 5 V CMOS logic series

Description The 54AC and 54ACT series represent over 60 product types with different high-speed CMOS functions, specifically designed to meet the radiation requirements of the aerospace industry. They include a large set of gates, flip-flops, multiplexers, counters, bus interfaces, and several

文件：403.9 Kbytes 頁數(shù)：28 Pages

STMICROELECTRONICS

意法半導(dǎo)體

16-BIT BUFFERS/DRIVERS WITH 3-STATE OUPUTS

Members of the Texas Instruments WidebusE Family Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up

文件：256.76 Kbytes 頁數(shù)：10 Pages

TI

德州儀器

16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family Inputs Are TTL-Voltage Compatible 3-State True Outputs Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-
m Process

文件：269.36 Kbytes 頁數(shù)：12 Pages

TI

德州儀器

16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family Inputs are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process Package Options Include

文件：221.81 Kbytes 頁數(shù)：9 Pages

TI

德州儀器

16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EP

文件：347.16 Kbytes 頁數(shù)：14 Pages

TI

德州儀器

16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up

文件：547.54 Kbytes 頁數(shù)：11 Pages

TI

德州儀器

18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process Members of the Texas Instruments WidebusE Family Inputs Are TTL-Voltage Compatible Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Flow-Through Architecture Optimizes PCB Layout Distributed VCC

文件：283.96 Kbytes 頁數(shù)：11 Pages

TI

德州儀器

18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family Inputs Are TTL-Voltage Compatible Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching N

文件：258.32 Kbytes 頁數(shù)：10 Pages

TI

德州儀器

20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPICE (Enhanced-Performance Implanted C

文件：229.57 Kbytes 頁數(shù)：9 Pages

TI

德州儀器