絲?。?strong>549；Package：SOT-23；PNP SILICON PLANAR MEDIUM POWER TRANSISTORS

FEATURES * Low equivalent on-resistance; RCE(sat) 250m? at 1A * 1 Amp continuous current

文件：122.88 Kbytes 頁數(shù)：2 Pages

ZETEX

絲印：549；Package：SSOT-3L；PNP Low-Saturation Transistor

Features ? This device is designed with high-current gain and low-saturation voltage with collector currents up to 2 A continuous. ? Sourced from process PB.

文件：272.85 Kbytes 頁數(shù)：7 Pages

ONSEMI

安森美半導(dǎo)體

絲印：54917；Package：VQFN；TPS54917 3-V to 4-V Input, 9-A, Small Synchronous Buck Switcher With Integrated FETs (SWIFT?)

1 Features 1? 13-mΩ MOSFET Switches for High Efficiency at 9-A Continuous Output ? Adjustable Output Voltage Down to 0.9 V With 1% Accuracy ? Externally Compensated for Design Flexibility ? Wide PWM Frequency: Fixed 350 kHz, 550 kHz, or Adjustable 280 kHz to 1.6 MHz ? Synchronizable to

文件：655.32 Kbytes 頁數(shù)：27 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/54917/marking.html">54917；Package：VQFN；TPS54917 3-V to 4-V Input, 9-A, Small Synchronous Buck Switcher With Integrated FETs (SWIFT?)

1 Features 1? 13-mΩ MOSFET Switches for High Efficiency at 9-A Continuous Output ? Adjustable Output Voltage Down to 0.9 V With 1% Accuracy ? Externally Compensated for Design Flexibility ? Wide PWM Frequency: Fixed 350 kHz, 550 kHz, or Adjustable 280 kHz to 1.6 MHz ? Synchronizable to

文件：655.32 Kbytes 頁數(shù)：27 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/54917/marking.html">54917；Package：VQFN；TPS54917 3-V to 4-V Input, 9-A, Small Synchronous Buck Switcher With Integrated FETs (SWIFT?)

1 Features 1? 13-mΩ MOSFET Switches for High Efficiency at 9-A Continuous Output ? Adjustable Output Voltage Down to 0.9 V With 1% Accuracy ? Externally Compensated for Design Flexibility ? Wide PWM Frequency: Fixed 350 kHz, 550 kHz, or Adjustable 280 kHz to 1.6 MHz ? Synchronizable to

文件：655.32 Kbytes 頁數(shù)：27 Pages

TI

德州儀器

絲印：54917；Package：VQFN；TPS54917 3-V to 4-V Input, 9-A, Small Synchronous Buck Switcher With Integrated FETs (SWIFT?)

1 Features 1? 13-mΩ MOSFET Switches for High Efficiency at 9-A Continuous Output ? Adjustable Output Voltage Down to 0.9 V With 1% Accuracy ? Externally Compensated for Design Flexibility ? Wide PWM Frequency: Fixed 350 kHz, 550 kHz, or Adjustable 280 kHz to 1.6 MHz ? Synchronizable to

文件：655.32 Kbytes 頁數(shù)：27 Pages

TI

德州儀器

The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter.

DESCRIPTION — The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter. It can be connected to operate with a conventional BCD output pattern or it can be connected to provide a 50% duty cycle

文件：306.59 Kbytes 頁數(shù)：3 Pages

ETCList of Unclassifed Manufacturers

未分類制造商

The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter.

DESCRIPTION — The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter. It can be connected to operate with a conventional BCD output pattern or it can be connected to provide a 50% duty cycle

文件：306.59 Kbytes 頁數(shù)：3 Pages

ETCList of Unclassifed Manufacturers

未分類制造商

The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter.

DESCRIPTION — The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter. It can be connected to operate with a conventional BCD output pattern or it can be connected to provide a 50 duty cycle outpu

文件：306.59 Kbytes 頁數(shù)：3 Pages

ETCList of Unclassifed Manufacturers

未分類制造商

DIVIDE-BY-TWELVE COUNTER

DESCRIPTION- The ’92 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divide-by-six. HIGH signals on the Master Reset (MR) inputs override the clocks and force all outputs to the LOW state.

文件：256.87 Kbytes 頁數(shù)：3 Pages

NSC

國半