絲?。?strong>542MLF；Package：SOIC；CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

文件：119.34 Kbytes 頁數(shù)：6 Pages

IDT

CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

文件：171.43 Kbytes 頁數(shù)：6 Pages

IDT

絲?。?strong>542MLF；Package：SOIC；CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

文件：119.34 Kbytes 頁數(shù)：6 Pages

IDT

絲?。?strong>542MLF；Package：SOIC；CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

文件：119.34 Kbytes 頁數(shù)：6 Pages

IDT

絲?。?strong>542MLF；Package：SOIC；CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

文件：119.34 Kbytes 頁數(shù)：6 Pages

IDT

CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

文件：171.43 Kbytes 頁數(shù)：6 Pages

IDT

Package：8-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 時鐘緩沖器，驅(qū)動器 描述：IC CLK BUFFER 1:2 156MHZ 8SOIC

Renesas Electronics America Inc

Package：8-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 時鐘緩沖器，驅(qū)動器 描述：IC CLK BUFFER 1:2 156MHZ 8SOIC

Renesas Electronics America Inc