HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS

文件：140.94 Kbytes 頁數(shù)：7 Pages

TI

德州儀器

Full Thickness Male Blades

文件：380.72 Kbytes 頁數(shù)：2 Pages

HEYCO

包裝：散裝 類別：創(chuàng)客/DIY，教育 教學套件 描述：SOLAR BUG KIT 2.0 FROM BROWN DOG

ADAFRUIT

包裝：散裝 類別：工具 配件 描述：BULL-PIN AND BOLT BAG - CANVAS

KLEIN

凱能

Customer Specification

Construction 1) Component 1 1 X 1 HOOKUP a) Conductor 16 (26/30) AWG Bare Copper 0.060 b) Insulation 0.016 Wall, Nom. PVC/ 0.005 Wall NYLON 0.102 (1) Print ALPHA WIRE-* P/N 541626 16 AWG E163871 (UL) TYPE TFFN 600V VW-1 * = Factory Code (2) Color(s) WHITE, BLACK, RED, GREEN, YE

文件：97.67 Kbytes 頁數(shù)：4 Pages

ALPHAWIRE

8-Bit Parallel-to-Serial Converter

General Description The ’165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputting occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; new da

文件：109.14 Kbytes 頁數(shù)：6 Pages

NSC

國半

8-Bit Parallel-to-Serial Converter

General Description The ’165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputting occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; new da

文件：109.14 Kbytes 頁數(shù)：6 Pages

NSC

國半

8-Bit Parallel-to-Serial Converter

General Description The ’165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputting occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; new da

文件：109.14 Kbytes 頁數(shù)：6 Pages

NSC

國半

SYNCHRONOUS DECADE RATE MULTIPLIER

DESCRIPTION 一 The 167 contains asynchronous decade counter and four decoding gates that serve to gate the clock through to the output at a sub- multiple of the clock frequency. The output pulse rate, relative to the clock frequency, is determined by signals applied to the Select (So 一 Ss) input

文件：297.73 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導體

SYNCHRONOUS DECADE RATE MULTIPLIER

DESCRIPTION 一 The 167 contains asynchronous decade counter and four decoding gates that serve to gate the clock through to the output at a sub- multiple of the clock frequency. The output pulse rate, relative to the clock frequency, is determined by signals applied to the Select (So 一 Ss) input

文件：297.73 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導體