Low Skew 1 to 4 Clock Buffer

The 524S is a low skew, single input to four output, LVCMOS clock buffer. The 524S has best in class additive phase Jitter of sub 50 fsec. ? Low additive phase jitter RMS: 50fs\n? Low cost clock buffer\n? ICLK is PDT and may be driven before VDD is applied\n? Input / Output clock frequency up to 200MHz\n? Ideal for networking clocks\n? Advanced, low power CMOS process\n? Extended temperature range (-40°C to +105°C);

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Low additive phase jitter RMS

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IDT

Package：8-UFDFN；包裝：卷帶（TR） 類別：集成電路（IC） 時鐘緩沖器，驅(qū)動器 描述：COL 2.00X2.00X0.50 MM, 0.50MM PI

Renesas Electronics America Inc

Package：8-SOIC（0.154"，3.90mm 寬）；包裝：托盤 類別：集成電路（IC） 時鐘緩沖器，驅(qū)動器 描述：MULTIMKT-TIMING

Renesas Electronics America Inc

Package：8-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 時鐘緩沖器，驅(qū)動器 描述：SOIC 4.90X3.90X1.50 MM, 1.27MM P

Renesas Electronics America Inc