| 型號 | 下載 訂購 | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
絲?。?a target="_blank" title="Marking" href="/32502bsa/marking.html">32502BSA；Package：CFP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/32502sra/marking.html">32502SRA；Package：CDIP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/32502ssa/marking.html">32502SSA；Package：CFP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/32502b2a/marking.html">32502B2A；Package：LCCC；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/32502bra/marking.html">32502BRA；Package：CDIP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲印：32502BSA；Package：CFP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲印：32502SRA；Package：CDIP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/32502ssa/marking.html">32502SSA；Package：CFP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/32502b2a/marking.html">32502B2A；Package：LCCC；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/32502bra/marking.html">32502BRA；Package：CDIP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI |
技術(shù)參數(shù)
- 間距：
11.12mm
- 結(jié)構(gòu)：
1x2P
- 每排PIN數(shù)：
2
- 排數(shù)：
1
- 額定電流：
15A
- 額定電壓：
300V
- 線規(guī) - AWG：
14~22
- 工作溫度范圍：
+105℃
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
LITTELFUSEFAREASTPTELTD |
24+ |
830 |
詢價(jià) | ||||
CURTIS |
25+ |
連接器 |
2963 |
就找我吧!--邀您體驗(yàn)愉快問購元件! |
詢價(jià) | ||
Curtis Industries |
23+ |
原廠封裝 |
98 |
只做原裝只有原裝現(xiàn)貨實(shí)報(bào) |
詢價(jià) | ||
24+ |
N/A |
82000 |
一級代理-主營優(yōu)勢-實(shí)惠價(jià)格-不悔選擇 |
詢價(jià) |
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