| 型號 | 下載 訂購 | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
絲?。?a target="_blank" title="Marking" href="/32502b2a/marking.html">32502B2A；Package：LCCC；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/32502bra/marking.html">32502BRA；Package：CDIP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/32502bsa/marking.html">32502BSA；Package：CFP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/32502sra/marking.html">32502SRA；Package：CDIP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/32502ssa/marking.html">32502SSA；Package：CFP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/32503b2a/marking.html">32503B2A；Package：LCCC；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/32503bra/marking.html">32503BRA；Package：CDIP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲印：32503BSA；Package：CFP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/32502b2a/marking.html">32502B2A；Package：LCCC；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/32502bra/marking.html">32502BRA；Package：CDIP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and 文件：1.58154 Mbytes 頁數(shù)：32 Pages | TI 德州儀器 | TI |
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
Simpson |
新 |
14 |
全新原裝 貨期兩周 |
詢價(jià) | |||
Simpson |
2022+ |
10 |
全新原裝 貨期兩周 |
詢價(jià) | |||
INTELDELCO |
24+ |
DIP-24 |
18 |
詢價(jià) | |||
原廠 |
16+ |
原廠封裝 |
10000 |
全新原裝正品,代理優(yōu)勢渠道供應(yīng),歡迎來電咨詢 |
詢價(jià) | ||
Parallax |
24+ |
SMD |
15600 |
開發(fā)板和工具包-其他處理器 |
詢價(jià) | ||
LITTELFUSE |
23+ |
NA |
1036 |
專做原裝正品,假一罰百! |
詢價(jià) | ||
KR |
20+ |
高通濾波器 |
50 |
詢價(jià) | |||
CTS |
2447 |
SMD |
100500 |
一級代理專營品牌!原裝正品,優(yōu)勢現(xiàn)貨,長期排單到貨 |
詢價(jià) | ||
TE |
25+ |
連接器 |
9049 |
就找我吧!--邀您體驗(yàn)愉快問購元件! |
詢價(jià) | ||
Transtector |
23+ |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價(jià) |
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