絲?。?strong>158；Package：SO-8；Low Power Dual Operational Amplifiers

■ Internally frequency compensated ■ Large DC voltage gain: 100dB ■ Wide bandwidth (unity gain): 1.1mHz (temperature compensated) ■ Very low supply current/op (500μA) essentially independent of supply voltage ■ Low input bias current: 20nA (temperature compensated) ■ Low input offset volta

文件：276.79 Kbytes 頁數(shù)：16 Pages

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絲印：158；Package：SO-8；Low Power Dual Operational Amplifiers

■ Internally frequency compensated ■ Large DC voltage gain: 100dB ■ Wide bandwidth (unity gain): 1.1mHz (temperature compensated) ■ Very low supply current/op (500μA) essentially independent of supply voltage ■ Low input bias current: 20nA (temperature compensated) ■ Low input offset volta

文件：276.79 Kbytes 頁數(shù)：16 Pages

STMICROELECTRONICS

意法半導(dǎo)體

絲?。?strong>158；Package：SO8；Low-power dual operational amplifiers

Features Frequency compensation implemented internally Large DC voltage gain: 100 dB Wide bandwidth (unity gain): 1.1 MHz (temperature compensated) Very low supply current per channel essentially independent of supply voltage Low input bias current: 20 nA (temperature compensated) Low input

文件：1.07811 Mbytes 頁數(shù)：25 Pages

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絲?。?a target="_blank" title="Marking" href="/15810gil/marking.html">15810GIL；Package：TSSOP；LOW PHASE NOISE T1/E1 CLOCK GENERATOR

Features ? Generates a T1 (1.544 MHz) or E1 (2.048 MHz) output clock from an 8kHz frame clock input ? Configurable jitter attenuation characteristics, excellent for use as a Stratum source de-jitter circuit ? VCXO-based clock generation ensures very low jitter and phase noise generation ? O

文件：410.26 Kbytes 頁數(shù)：12 Pages

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絲?。?a target="_blank" title="Marking" href="/15810gil/marking.html">15810GIL；Package：TSSOP；LOW PHASE NOISE T1/E1 CLOCK GENERATOR

Features ? Generates a T1 (1.544 MHz) or E1 (2.048 MHz) output clock from an 8kHz frame clock input ? Configurable jitter attenuation characteristics, excellent for use as a Stratum source de-jitter circuit ? VCXO-based clock generation ensures very low jitter and phase noise generation ? O

文件：410.26 Kbytes 頁數(shù)：12 Pages

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絲?。?a target="_blank" title="Marking" href="/15810/marking.html">15810；Package：H2PAK-2；N-channel 100 V, 0.0034 Ω typ., 110 A, STripFET? F7 Power MOSFET in a H2PAK-2 package

Features ? 100 avalanche tested ? Ultra low on-resistance Applications ? Switching applications Description This N-channel Power MOSFETs utilize STripFET? F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal ca

文件：969.93 Kbytes 頁數(shù)：16 Pages

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絲印：15810；Package：TO-220；N-channel 100 V, 0.0036 Ω typ., 110 A, STripFET? F7 Power MOSFET in a TO-220 package

Features ? 100 avalanche tested ? Ultra low on-resistance Applications ? Switching applications Description This N-channel Power MOSFETs utilizes STripFET? F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal c

文件：357.98 Kbytes 頁數(shù)：13 Pages

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絲?。?a target="_blank" title="Marking" href="/1589a/marking.html">1589A；Package：DFN-103x3；Low Voltage Synchronous Buck Controller

文件：206.52 Kbytes 頁數(shù)：10 Pages

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絲印：1589A；Package：DFN-103x3；Low Voltage Synchronous Buck Controller

文件：94.07 Kbytes 頁數(shù)：10 Pages

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絲?。?a target="_blank" title="Marking" href="/1589b/marking.html">1589B；Package：DFN-103x3；Low Voltage Synchronous Buck Controller

文件：94.07 Kbytes 頁數(shù)：10 Pages

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安森美半導(dǎo)體